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Compact and accurate stochastic circuits with shared random number sources.

, , , , и . ICCD, стр. 361-366. IEEE Computer Society, (2014)

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Tsuyoshi Takagi

Tsuyoshi Matsuda

 

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Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , и . VLSI-SoC (Selected Papers), том 249 из IFIP, стр. 301-316. Springer, (2006)An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis., , , и . ITC-Asia, стр. 55-60. IEEE, (2019)Logic simplification by minterm complement for error tolerant application., , , и . ICCD, стр. 94-100. IEEE Computer Society, (2015)A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties., и . DELTA, стр. 293-296. IEEE Computer Society, (2010)On the derivation of a minimum test set in high quality transition testing., и . LATW, стр. 1-6. IEEE, (2009)Safe clocking register assignment in datapath synthesis., , и . ICCD, стр. 120-127. IEEE Computer Society, (2008)Compact and accurate stochastic circuits with shared random number sources., , , , и . ICCD, стр. 361-366. IEEE Computer Society, (2014)Scheduling algorithm in datapath synthesis for long duration transient fault tolerance., , , , и . DFT, стр. 128-133. IEEE Computer Society, (2014)Efficient path delay test generation based on stuck-at test generation using checker circuitry., , , и . ICCAD, стр. 418-423. IEEE Computer Society, (2007)Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation., , и . ETS, стр. 48-53. IEEE Computer Society, (2005)