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26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection., , , , , , , , , and . ISSCC, page 444-445. IEEE, (2017)The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor., , , , , , , , , and 4 other author(s). ISSCC, page 102-103. IEEE, (2010)Session 3 overview: Processors: High performance digital subcommittee., and . ISSCC, page 54-55. IEEE, (2012)The POWER8TM processor: Designed for big data, analytics, and cloud environments., , , , , , , , , and 10 other author(s). ICICDT, page 1-4. IEEE, (2014)On-chip Timing Uncertainty Measurements on IBM Microprocessors., , , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2008)Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor., , , , and . ISSCC, page 298-604. IEEE, (2007)Design methodology for the IBM POWER7 microprocessor., , , , , , , , , and 15 other author(s). IBM J. Res. Dev., 55 (3): 9 (2011)Power/performance optimization of many-core processor SoCs., , , , , and . ISSCC, page 508-509. IEEE, (2012)The opportunity cost of low power design: a case study in circuit tuning., , , , and . ISLPED, page 133-138. ACM, (2009)POWER7TM local clocking and clocked storage elements., , , , , , , and . ISSCC, page 178-179. IEEE, (2010)