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DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.

C. Cheng, C. Holtz, A. Kahng, B. Lin, and U. Mallappa. ACM Trans. Design Autom. Electr. Syst., 28 (4): 52:1-52:31 (July 2023)

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Mallappa Yerasi

Sumesh Udayakumaran

Andreyasa Udayana

Uday Hattim Mahmod Sallawi

Other publications of authors with the same name

PARSAC: Fast, Human-quality Floorplanning for Modern SoCs with Complex Design Constraints.H. Mostafa, U. Mallappa, M. Galkin, M. Phielipp, and S. Majumdar. CoRR, (2024)GRA-LPO: Graph Convolution Based Leakage Power Optimization.U. Mallappa, and C. Cheng. ASP-DAC, page 697-702. ACM, (2021)JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.U. Mallappa, C. Cheng, and B. Lin. IEEE Des. Test, 39 (6): 16-27 (2022)RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization.U. Mallappa, S. Pratty, and D. Brown. DATE, page 120-123. IEEE, (2022)Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis.A. Kahng, U. Mallappa, and L. Saul. ICCD, page 603-612. IEEE Computer Society, (2018)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.C. Cheng, C. Holtz, A. Kahng, B. Lin, and U. Mallappa. ACM Trans. Design Autom. Electr. Syst., 28 (4): 52:1-52:31 (July 2023)TermiNETor: Early Convolution Termination for Efficient Deep Neural Networks.U. Mallappa, P. Gangwar, B. Khaleghi, H. Yang, and T. Rosing. ICCD, page 635-643. IEEE, (2022)Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.T. Ajayi, V. Chhabria, M. Fogaça, S. Hashemi, A. Hosny, A. Kahng, M. Kim, J. Lee, U. Mallappa, M. Neseem and 11 other author(s). DAC, page 76. ACM, (2019)Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.U. Mallappa, C. Cheng, and B. Lin. IEEE Embed. Syst. Lett., 14 (4): 175-178 (2022)PatterNet: explore and exploit filter patterns for efficient deep neural networks.B. Khaleghi, U. Mallappa, D. Yaldiz, H. Yang, M. Shah, J. Kang, and T. Rosing. DAC, page 223-228. ACM, (2022)

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Disambiguation of "Mallappa, Uday"

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DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.

Please choose a person to relate this publication to

Mallappa Yerasi

Sumesh Udayakumaran

Andreyasa Udayana

Uday Hattim Mahmod Sallawi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mallappa, Uday"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.

Please choose a person to relate this publication to

Mallappa Yerasi

Sumesh Udayakumaran

Andreyasa Udayana

Uday Hattim Mahmod Sallawi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.