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Другие публикации лиц с тем же именем

Fault tolerant FPGA processor based on runtime reconfigurable modules., и . European Test Symposium, стр. 1-6. IEEE Computer Society, (2012)Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units., , , и . IEEE Trans. Computers, 55 (11): 1449-1457 (2006)Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs., , , , и . DFT, стр. 1-6. IEEE, (2021)Functional Self-Testing for Bus-Based Symmetric Multiprocessors., , , и . DATE, стр. 1304-1309. ACM, (2008)Deterministic software-based self-testing of embedded processor cores., , , , и . DATE, стр. 92-96. IEEE Computer Society, (2001)An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers., , , и . VTS, стр. 252-259. IEEE Computer Society, (1999)A scrubbing scheduling approach for reliable FPGA multicore processors with real-time constraints., и . DFT, стр. 1-4. IEEE Computer Society, (2017)An Effective BIST Scheme for Arithmetic Logic Units., , , и . ITC, стр. 868-877. IEEE Computer Society, (1997)An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm., , и . ARC, том 10824 из Lecture Notes in Computer Science, стр. 166-177. Springer, (2018)Online error detection in multiprocessor chips: A test scheduling study., , , , и . IOLTS, стр. 169-172. IEEE, (2013)