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Disambiguation of "Fujiwara, Hideo"

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A non-scan DFT method at register-transfer level to achieve complete fault efficiency.

, , , and . ASP-DAC, page 599-604. ACM, (2000)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

Handling the pin overhead problem of DFTs for high-quality and at-speed tests., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)SPIRIT: a highly robust combinational test generation algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (12): 1446-1458 (2002)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Test research in Japan., , , , , and . IEEE Des. Test, 5 (5): 60-79 (1988)A Test Methodology for Interconnect Structures of LUT-based FPGAs., , , , and . Asian Test Symposium, page 68-74. IEEE Computer Society, (1996)New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency., , and . Asian Test Symposium, page 263-268. IEEE Computer Society, (1999)Instruction-Based Delay Fault Self-Testing of Processor Cores., , , and . VLSI Design, page 933-. IEEE Computer Society, (2004)Localized random access scan: Towards low area and routing overhead., , , and . ASP-DAC, page 565-570. IEEE, (2008)Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis., , and . Asian Test Symposium, page 86-. IEEE Computer Society, (2002)Spirit: satisfiability problem implementation for redundancy identification and test generation., and . Asian Test Symposium, page 171-178. IEEE Computer Society, (2000)