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Disambiguation of "Beerel, Peter A."

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Formal Verification of Flow Equivalence in Desynchronized Designs.

, , , and . ASYNC, page 54-62. IEEE, (2020)

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Peter A Ehrl

Peter A Schmid

Peter A Wuffli

Peter A Gloor

Peter A Ehrl

 

Other publications of authors with the same name

Asynchronous Design for High-Speed and Low-Power Circuits.. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 669. Springer, (2006)Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)., , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 613-618. ACM, (2023)A memory allocation and assignment method using multiway partitioning., , and . SoCC, page 143-144. IEEE, (2004)Characterizing Sparse Connectivity Patterns in Neural Networks, , , and . (2017)cite arxiv:1711.02131Comment: Presented at the 2018 Information Theory and Applications Workshop, San Diego, California.A polynomial time flow for implementing free-choice Petri-nets., , and . ICCD, page 227-234. IEEE Computer Society, (2012)Deep-n-Cheap: An Automated Search Framework for Low Complexity Deep Learning., , , and . ACML, volume 129 of Proceedings of Machine Learning Research, page 273-288. PMLR, (2020)A low latency SISO with application to broadband turbo decoding., and . IEEE J. Sel. Areas Commun., 19 (5): 860-870 (2001)Proteus: An ASIC Flow for GHz Asynchronous Designs., , and . IEEE Des. Test Comput., 28 (5): 36-51 (2011)Neural Network Training with Approximate Logarithmic Computations., , and . ICASSP, page 3122-3126. IEEE, (2020)High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog., and . CPA, volume 63 of Concurrent Systems Engineering Series, page 275-288. IOS Press, (2005)