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Disambiguation of "Chattopadhyay, Anupam"

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Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays.

, , and . VLSI-SoC, page 1-6. IEEE, (2016)

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Anupam Chattopadhyay

Anupam Singh

Anupam Karmakar

Anupam Sengupta

Dhrupadi Chattopadhyay

 

Other publications of authors with the same name

SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing., , , , and . ISLPED, page 1-6. IEEE, (2019)Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design., , , and . DATE, page 547-552. EDA Consortium San Jose, CA, USA / ACM DL, (2013)ReVAMP: ReRAM based VLIW architecture for in-memory computing., , and . DATE, page 782-787. IEEE, (2017)Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor., , and . VLSI-SoC, page 95-100. IEEE, (2018)A Security Model for Intelligent Vehicles and Smart Traffic Infrastructure., , , and . Intelligent Vehicles Symposium, page 162-167. IEEE, (2018)One Word/Cycle HC-128 Accelerator via State-Splitting Optimization., , , and . INDOCRYPT, volume 8885 of Lecture Notes in Computer Science, page 283-303. Springer, (2014)Area-constrained technology mapping for in-memory computing using ReRAM devices., , and . ASP-DAC, page 69-74. IEEE, (2017)New techniques for fault-tolerant decomposition of Multi-Controlled Toffoli gate., , , and . CoRR, (2019)On Hardware Implementation of Tang-Maitra Boolean Functions., , , and . WAIFI, volume 11321 of Lecture Notes in Computer Science, page 111-127. Springer, (2018)Logic-In-Memory Architecture For Min/Max Search., , , and . ICECS, page 853-856. IEEE, (2018)