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A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform.

C. Ding, Y. Huan, H. Jia, Y. Yan, F. Yang, L. Liu, M. Shen, Z. Zou, and L. Zheng. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (5): 1990-2001 (2022)

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Yuxiang Ye

Yuxiang Zhang

Yuxiang Zhou

Yuxiang Dong

Other publications of authors with the same name

A Smart Dental Health-IoT Platform Based on Intelligent Hardware, Deep Learning, and Mobile Terminal.L. Liu, J. Xu, Y. Huan, Z. Zou, S. Yeh, and L. Zheng. IEEE J. Biomed. Health Informatics, 24 (3): 898-906 (2020)Graph-Based Spatio-Temporal Backpropagation for Training Spiking Neural Networks.Y. Yan, H. Chu, X. Chen, Y. Jin, Y. Huan, L. Zheng, and Z. Zou. AICAS, page 1-4. IEEE, (2021)A 3D Tiled Low Power Accelerator for Convolutional Neural Network.Y. Huan, J. Xu, L. Zheng, H. Tenhunen, and Z. Zou. ISCAS, page 1-5. IEEE, (2018)A multiplication reduction technique with near-zero approximation for embedded learning in IoT devices.Y. Huan, Y. Qin, Y. You, L. Zheng, and Z. Zou. SoCC, page 102-107. IEEE, (2016)MCU-Enabled Epileptic Seizure Detection System With Compressed Learning.L. Qian, J. Lu, W. Li, Y. Huan, Y. Sun, L. Zheng, and Z. Zou. IEEE Internet Things J., 11 (5): 8771-8782 (2024)A Neuromorphic Processing System for Low-Power Wearable ECG Classification.H. Chu, H. Jia, Y. Yan, Y. Jin, L. Qian, L. Gan, Y. Huan, L. Zheng, and Z. Zou. BioCAS, page 1-5. IEEE, (2021)A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks.J. Xu, Y. Huan, L. Zheng, and Z. Zou. SoCC, page 43-48. IEEE, (2018)Universal and Convenient Optimization Strategies for Three-Terminal Memristors.K. Yang, Y. Huan, J. Xu, Z. Zou, Y. Zhan, L. Zheng, and F. Seoane. IEEE Access, (2018)QoS based RFID system for smart assembly workshop.C. Zhai, Z. Zou, Y. Qin, N. Ma, Y. Huan, Q. Chen, L. Zheng, and H. Tenhunen. RFID-TA, page 138-143. IEEE, (2016)An ASIC Design of Multi-Electrode Digital Basket Catheter Systems with Reconfigurable Compressed Sampling.H. Chu, Y. Huan, D. Bao, B. Källbäck, Y. Qin, Z. Zou, and L. Zheng. SoCC, page 124-129. IEEE, (2018)

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Disambiguation of "Huan, Yuxiang"

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A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform.

Please choose a person to relate this publication to

Yuxiang Ye

Yuxiang Zhang

Yuxiang Zhou

Yuxiang Zhou

Yuxiang Dong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Huan, Yuxiang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform.

Please choose a person to relate this publication to

Yuxiang Ye

Yuxiang Zhang

Yuxiang Zhou

Yuxiang Zhou

Yuxiang Dong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform.