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VLSI Concurrent Error Correcting Adders and Multipliers., and . DFT, page 287-294. IEEE Computer Society, (1993)A systolic array for 2-D DFT and 2-D DCT., and . ASAP, page 123-131. IEEE, (1994)Parallel Counters.. IEEE Trans. Computers, 22 (11): 1021-1024 (1973)A Spanning Tree Carry Lookahead Adder., and . IEEE Trans. Computers, 41 (8): 931-939 (1992)Dadda Multiplier designs using memristors., and . ICICDT, page 1-4. IEEE, (2017)The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-22. Springer, (2007)The hazard-free superscalar pipeline fast fourier transform algorithm and architecture., , and . VLSI-SoC, page 194-199. IEEE, (2007)Editorial.. VLSI Signal Processing, 1 (1): 5 (1989)The Sign/Logarithm Number System., and . IEEE Trans. Computers, 24 (12): 1238-1242 (1975)Quantifying academic placer performance on custom designs., , , , , and . ISPD, page 91-98. ACM, (2011)