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Disambiguation of "Beerel, Peter A."

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BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from Scratch.

, , , , and . DATE, page 588-591. IEEE, (2022)

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Peter A Ehrl

Peter A Schmid

Peter A Wuffli

Peter A Ehrl

Peter A Gloor

 

Other publications of authors with the same name

Characterizing Sparse Connectivity Patterns in Neural Networks, , , and . (2017)cite arxiv:1711.02131Comment: Presented at the 2018 Information Theory and Applications Workshop, San Diego, California.Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)., , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 613-618. ACM, (2023)Slack matching mode-based asynchronous circuits for average-case performance., and . ICCAD, page 219-225. IEEE, (2013)Neural Network Training with Approximate Logarithmic Computations., , and . ICASSP, page 3122-3126. IEEE, (2020)Proteus: An ASIC Flow for GHz Asynchronous Designs., , and . IEEE Des. Test Comput., 28 (5): 36-51 (2011)Deep-n-Cheap: An Automated Search Framework for Low Complexity Deep Learning., , , and . ACML, volume 129 of Proceedings of Machine Learning Research, page 273-288. PMLR, (2020)SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces., and . CPA, volume 68 of Concurrent Systems Engineering Series, page 287-302. IOS Press, (2011)High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog., and . CPA, volume 63 of Concurrent Systems Engineering Series, page 275-288. IOS Press, (2005)A memory allocation and assignment method using multiway partitioning., , and . SoCC, page 143-144. IEEE, (2004)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , and . ASYNC, page 124-131. IEEE Computer Society, (2015)