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Programming Model to Develop Supercomputer Combinatorial Solvers.

, , , , , , , and . ICPP Workshops, page 171-179. IEEE Computer Society, (2017)

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Reconfigurable Hardware Acceleration of Canonical Graph Labelling., , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 302-313. Springer, (2007)A General-Purpose Method for Faithfully Rounded Floating-Point Function Approximation in FPGAs.. ARITH, page 42-49. IEEE, (2015)Automated framework for FPGA-based parallel genetic algorithms., , , and . FPL, page 1-7. IEEE, (2014)Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters., , , and . FPT, page 233-240. IEEE, (2010)Non-deterministic event brokered computing., , , , , , , , , and . HEART, page 84-86. ACM, (2022)A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU., , and . ICNC, page 175-181. IEEE Computer Society, (2012)Accelerating Quadrature Methods for Option Valuation., , and . FCCM, page 29-36. IEEE Computer Society, (2009)Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware., and . FCCM, page 3-12. IEEE Computer Society, (2007)FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers., and . FPL, page 77-82. IEEE Computer Society, (2010)Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes., , , , and . FPL, page 81-87. IEEE, (2019)