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Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning.

, , , and . SLIP, page 8-15. IEEE, (2021)

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Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning., , , and . SLIP, page 8-15. IEEE, (2021)Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization., , and . ASP-DAC, page 288-293. IEEE, (2022)NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model., , , , , , , and . ISPD, page 44-52. ACM, (2023)Large Language Model (LLM) for Standard Cell Layout Design Optimization., and . CoRR, (2024)Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (6): 1178-1191 (2021)Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Novel Transformer Model Based Clustering Method for Standard Cell Design Automation., , , , , , and . ISPD, page 195-203. ACM, (2024)Incremental transient simulation of power grid., , , and . ISPD, page 93-100. ACM, (2014)IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop., and . ICCAD, page 1-8. ACM, (2019)A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT., , , and . ICCAD, page 158:1-158:8. IEEE, (2020)