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Disambiguation of "Kosuge, Atsutake"

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A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna.

, , , , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory., , , , , , , and . VLSIC, page 128-. IEEE, (2015)Analytical thruchip inductive coupling channel design optimization., , , , , and . ASP-DAC, page 731-736. IEEE, (2016)A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application., , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers., , , , and . HCS, page 1-14. IEEE, (2022)A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias., , , , and . ICECS 2022, page 1-4. IEEE, (2022)A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers., , , , , and . ASP-DAC, page 91-92. IEEE, (2013)A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS., , , , and . ASP-DAC, page 180-181. ACM, (2023)Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format., , , , and . NEWCAS, page 99-103. IEEE, (2022)An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique., , , and . SAS, page 1-6. IEEE, (2022)A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna., , , , , , and . A-SSCC, page 1-3. IEEE, (2021)