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A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology., , , , , , , , , и 8 other автор(ы). ESSCIRC, стр. 237-240. IEEE, (2022)A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology., , , , , , , , , и 8 other автор(ы). ESSCIRC, стр. 333-336. IEEE, (2023)A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration., , , , , и . ISCAS, стр. 1-5. IEEE, (2020)A 0.6-3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters., , , , , , и . ESSCIRC, стр. 299-302. IEEE, (2015)A 5 GHz CT $\Delta\sum$ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS., , , , и . NORCAS, стр. 1-4. IEEE, (2019)A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs., , , , , , и . NorCAS, стр. 1-6. IEEE, (2020)Digital background calibration in continuous-time delta-sigma analog to digital converters., , , , и . NORCAS, стр. 1-4. IEEE, (2015)A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI., , , , и . ESSCIRC, стр. 179-180. IEEE, (2017)