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Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1933-1946 (2019)Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1555-1563 (2015)A Cross-layer Cognitive Radio Testbed for the Evaluation of Spectrum Sensing Receiver and Interference Analysis., , , , , , и . CrownCom, стр. 1-6. IEEE, (2008)Subthreshold current mode matrix determinant computation for analog signal processing., , , , , и . ISCAS, стр. 1260-1263. IEEE, (2010)A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit., , , , , , , и . IEEE J. Solid State Circuits, 57 (1): 236-244 (2022)3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology., , , , , , , , , и 1 other автор(ы). CICC, стр. 1-7. IEEE, (2022)24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 338-340. IEEE, (2021)Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process., , , , , , , , , и 9 other автор(ы). VLSI Technology and Circuits, стр. 363-364. IEEE, (2022)A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application., , , , и . VLSI Circuits, стр. 1-2. IEEE, (2021)Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_MIN$ Improvement and Energy Saving., , , , , , , и . IEEE J. Solid State Circuits, 54 (3): 896-906 (2019)