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Memory-Centric Architecture of Neural Processing Unit for Edge Device., , , , and . ISOCC, page 240-241. IEEE, (2021)Efficient final output feature map processing method supporting real-time object detection and recognition., , , , and . ISOCC, page 324-325. IEEE, (2020)A Novel Low-Cost High-Throughput CAVLC Decoder for H.264/AVC., , , , and . IEICE Trans. Inf. Syst., 94-D (4): 895-904 (2011)A 4-way pipelined processing architecture for three-step search block-matching motion estimation., and . IEEE Trans. Consumer Electronics, 50 (2): 674-681 (2004)Implementation of a Round Robin Processing Element for Deep Learning Accelerator., , , and . ISOCC, page 302-303. IEEE, (2020)Object Detection Network Robust to Local Illumination Variations., , , and . ISOCC, page 87-88. IEEE, (2021)Improved mutation method for providing high genetic diversity of genetic algorithm processor., and . IEICE Electron. Express, 9 (9): 822-827 (2012)Hardware implementation of fast traffic sign recognition for intelligent vehicle system., , , and . ISOCC, page 161-162. IEEE, (2016)An efficient recursive cell architecture of modified Euclid's algorithm for decoding Reed-Solomon codes., and . IEEE Trans. Consumer Electronics, 48 (4): 845-849 (2002)Implementation of a H.264/AVC SVC decoder with multi-symbol prediction CAVLC for advanced T-DMB receiver., , , , and . IEEE Trans. Consumer Electron., 56 (4): 2819-2825 (2010)