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Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding.

, , , , and . MWSCAS, page 1-4. IEEE, (2016)

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Post-processing of supergate networks aiming cell layout optimization., , , , , , and . ISCAS, page 1-4. IEEE, (2017)Area-Aware Design of Static CMOS Complex Gates., , , , and . NEWCAS, page 282-286. IEEE, (2018)Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool., , , , , and . LASCAS, page 355-358. IEEE, (2016)A post-processing methodology to improve the automatic design of CMOS gates at layout-level., , , , , , and . ICECS, page 42-45. IEEE, (2017)Transistor placement strategies for non-series-parallel cells., , , , , and . MWSCAS, page 523-526. IEEE, (2017)Physical design of supergate cells aiming geometrical optimizations., , , , , and . MWSCAS, page 1-4. IEEE, (2016)A parallel Motion Estimation solution for heterogeneous System on Chip., , , , , , and . SBCCI, page 1-6. IEEE, (2016)Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding., , , , and . MWSCAS, page 1-4. IEEE, (2016)