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Disambiguation of "Brea, Víctor M."

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An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 844-848 (2022)

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Brea Gerson

Pádraig Breatnach

Andrea Bréard

Víctor Farías

Víctor Castaño

 

Other publications of authors with the same name

Design of a 5-bit Signed SRAM-based In-Memory Computing Cell for Deep Learning Models., , , , and . ISCAS, page 702-706. IEEE, (2022)Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models., , , , and . ECCTD, page 92-95. IEEE, (2007)Fast Time-Domain Super-Resolution for Single-Shot Multi- Path ToF Imaging., , , , and . ICECS 2022, page 1-4. IEEE, (2022)Feature detection and matching on an SIMD/MIMD hybrid embedded processor., , and . CVPR Workshops, page 21-26. IEEE Computer Society, (2012)Effect of temporal and spatial noise on the performance of hardware oriented background extraction algorithms., , , and . NEWCAS, page 45-48. IEEE, (2017)In-pixel ADC for a vision architecture on CMOS-3D technology., , , , , and . 3DIC, page 1-7. IEEE, (2010)Pixel-Level Snakes., , , and . ICPR, page 1640-1643. IEEE Computer Society, (2000)Downsampling GAN for Small Object Data Augmentation., , , , and . CAIP (1), volume 14184 of Lecture Notes in Computer Science, page 89-98. Springer, (2023)Scale- and rotation- invariant feature detectors on Cellular Processor Arrays., , , and . ISCAS, page 2657-2660. IEEE, (2012)A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing., , , , and . ISCAS (4), page 3922-3925. IEEE, (2005)