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HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference.

, , , , , and . FCCM, page 50-59. IEEE, (2021)

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Squeezeformer: An Efficient Transformer for Automatic Speech Recognition., , , , , , , and . NeurIPS, (2022)Comparing Analytical Modeling with Simulation for Network Processors: A Case Study., , , and . DATE, page 20256-20261. IEEE Computer Society, (2003)Megatrends and EDA 2017., , , , , , and . DAC, page 21-22. IEEE, (2007)Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant?, , , , , , , and . DAC, page 479. ACM, (2002)Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express., , , , and . PARELEC, page 129-134. IEEE Computer Society, (2004)Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation.. DAC, page 308-313. ACM Press, (1989)What is the Next Big Productivity Boost for Designers? (Panel Abstract).. DAC, page 141. ACM Press, (1993)Why is ATPG Easy?, , and . DAC, page 22-28. ACM Press, (1999)Challenges in code generation for embedded processors., , , , , , , and . Code Generation for Embedded Processors, page 48-64. Kluwer, (1994)An automated exploration framework for FPGA-based soft multiprocessor systems., , , and . CODES+ISSS, page 273-278. ACM, (2005)