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Design exploration of hybrid caches with disparate memory technologies.

, , , , , and . ACM Trans. Archit. Code Optim., 7 (3): 15:1-15:34 (2010)

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Power and performance of read-write aware Hybrid Caches with non-volatile memories., , , , and . DATE, page 737-742. IEEE, (2009)Characterizing and Improving the Performance of Bioinformatics Workloads on the POWER5 Architecture., , , and . IISWC, page 89-97. IEEE Computer Society, (2007)Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems., , , and . IEEE Trans. Computers, 53 (3): 288-307 (2004)Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters., , and . ISHPC, volume 2327 of Lecture Notes in Computer Science, page 78-92. Springer, (2002)Poster reception - Pairwise alignments on the cell processor., , and . SC, page 171. ACM Press, (2006)Realizing the performance potential of the virtual interface architecture., , and . International Conference on Supercomputing, page 184-192. ACM, (1999)Power-efficient time-sensitive mapping in heterogeneous systems., , , , , and . PACT, page 23-32. ACM, (2012)Willow: A Scalable Shared Memory Multiprocessor., , , and . SC, page 336-345. IEEE Computer Society, (1992)Enigma: architectural and operating system support for reducing the impact of address translation., , , and . ICS, page 159-168. ACM, (2010)Mambo: a full system simulator for the PowerPC architecture., , , , , , , , , and 4 other author(s). SIGMETRICS Perform. Evaluation Rev., 31 (4): 8-12 (2004)