( en | de | ru )

 

Disambiguation of "Fesquet, Laurent"

Author of the publication

copydeleteadd this publication to your clipboard
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case.

, , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 137-149. Springer, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Laurent Bartholdi

Laurent Ntahuga

Thomas Laurent

Thomas Laurent

Laurent Herschke

 

Other publications of authors with the same name

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA., , , , , and . ReCoSoC, page 15-22. Univ. Montpellier II, (2007)Simple tri-state logic Trojans able to upset properties of ring oscillators., , , and . DTIS, page 1-6. IEEE, (2016)Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems., , , , , and . ISCAS, page 1-5. IEEE, (2018)Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring., , , , and . DCIS, page 1-5. IEEE, (2018)A Novel Event Based Image Sensor with spacial and temporal redundancy suppression., , , and . NEWCAS, page 238-241. IEEE, (2020)Event-based design strategy for circuit electromagnetic compatibility., , and . EBCCSP, page 1-7. IEEE, (2017)Distributed asynchronous controllers for clock management in low power systems., , , , , and . ICECS, page 379-382. IEEE, (2014)MOOC and practices in electrical and information engineering: Complementary approaches., and . ITHET, page 1-4. IEEE, (2016)Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits., , , and . PATMOS, page 229-234. IEEE, (2016)Towards consistency checking between HDL and UPF descriptions., , and . FDL, page 1-6. IEEE, (2017)