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Programmable Routing Tables for Degradable Torus-Based Networks on Chips.

, , and . ISCAS, page 1065-1068. IEEE, (2007)

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Programmable Routing Tables for Degradable Torus-Based Networks on Chips., , and . ISCAS, page 1065-1068. IEEE, (2007)Designing a resilient skip-stop schedule in rapid rail transit using a simulation-based optimization methodology., , , and . Oper. Res., 21 (3): 1691-1721 (2021)A reconfigurable online BIST for combinational hardware using digital neural networks., , , and . European Test Symposium, page 139-144. IEEE Computer Society, (2010)Degradable mesh-based on-chip networks using programmable routing tables., , , and . IEICE Electron. Express, 4 (10): 332-339 (2007)High Level Synthesis of Degradable ASICs Using Virtual Binding., , , , and . VTS, page 311-317. IEEE Computer Society, (2007)Configurable Systolic Matrix Multiplication., , , and . VLSID, page 336-341. IEEE Computer Society, (2014)A partitioning approach to improve reconfigurable neuron-inspired online BIST., , , and . IOLTS, page 173-178. IEEE Computer Society, (2010)A novel graceful degradable routing algorithm for 3D on-chip networks., , , and . INA-OCMC@HiPEAC, page 17-20. ACM, (2012)Experimental Validation of CT-Snubber for Multichip SiC MOSFET Power Module., , , , and . MWSCAS, page 419-423. IEEE, (2020)