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Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors., , , and . HPCA, page 424-434. IEEE, (2020)Freeway: Maximizing MLP for Slice-Out-of-Order Execution., , and . HPCA, page 558-569. IEEE, (2019)Ghost loads: what is the cost of invisible speculation?, , , , , and . CF, page 153-163. ACM, (2019)Non-Speculative Load-Load Reordering in TSO., , , and . ISCA, page 187-200. ACM, (2017)Rethinking Dynamic Instruction Scheduling and Retirement for Efficient Microarchitectures.. Uppsala University, Sweden, (2020)base-search.net (ftuppsalauniv:oai:DiVA.org:uu-403675).Exploring the Performance Limits of Out-of-order Commit., , and . Conf. Computing Frontiers, page 211-220. ACM, (2017)Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores., , and . ACM Trans. Archit. Code Optim., 19 (2): 25:1-25:28 (2022)Constructing a Weak Memory Model., , , , and . ISCA, page 124-137. IEEE Computer Society, (2018)Non-Speculative Load Reordering in Total Store Ordering., , , and . IEEE Micro, 38 (3): 48-57 (2018)Performance per power optimum cache architecture for embedded applications, a design space exploration., , and . NESEA, page 1-6. IEEE Computer Society, (2011)