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Disambiguation of "Shibata, Tsugumichi"

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10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control.

, , , , , and . ISOCC, page 357-360. IEEE, (2011)

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Daisuke Shibata

Tomohiro Shibata

 

Other publications of authors with the same name

An Indoor Positioning with a Neural Network Model of TensorFlow for Machine Learning., , and . ISPACS, page 1-2. IEEE, (2021)10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control., , , , , and . ISOCC, page 357-360. IEEE, (2011)An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU., , , , , , and . IEICE Trans. Electron., 97-C (7): 697-706 (2014)A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase., , and . ISPACS, page 442-446. IEEE, (2018)A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator., , , and . IEEE J. Solid State Circuits, 38 (2): 192-197 (2003)A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation., , , , , , , and . IEICE Trans. Electron., 88-C (6): 1225-1232 (2005)An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor., , , and . ISCAS, page 938-941. IEEE, (2015)A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON., , , , , and . A-SSCC, page 305-308. IEEE, (2011)Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction., , , , , and . GLOBECOM, page 1-5. IEEE, (2011)High-bit-rate low-power decision circuit using InP/InGaAs HBT technology master-slave D-type flip-flop., , , , , , and . ESSCIRC, page 355-358. IEEE, (2004)