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ArChiVED: Architectural checking via event digests for high performance validation.

, , , , and . DATE, page 1-6. European Design and Automation Association, (2014)

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Ontology-Based Tools in the Service of Hardware Verification., , , , , , , , and . SEKE, page 303-308. Knowledge Systems Institute Graduate School, (2010)Facing the challenge of new design features: an effective verification approach., , , , and . DAC, page 842-847. ACM, (2011)Checking architectural outputs instruction-by-instruction on acceleration platforms., , , , and . DAC, page 955-961. ACM, (2012)Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms., , , , , , , and . ICCAD, page 311-317. IEEE, (2013)Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation., , , , , , and . ICCD, page 544-551. IEEE Computer Society, (2016)Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification., , , , , , and . DAC, page 24:1-24:6. ACM, (2016)Accelerators and emulators: Can they become the platform of choice for hardware verification?, and . DATE, page 430. IEEE, (2012)ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors., , , and . IOLTS, page 72-77. IEEE, (2016)SLAM: SLice And Merge - Effective Test Generation for Large Systems., , , , and . Haifa Verification Conference, volume 8244 of Lecture Notes in Computer Science, page 151-165. Springer, (2013)Special Session on Debugging., , , and . Haifa Verification Conference, volume 6504 of Lecture Notes in Computer Science, page 24-28. Springer, (2010)