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Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking.

, , , , , and . ISCAS, IEEE, (2006)

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Performance analysis using pipeline visualization., , , , and . ISPASS, page 18-21. IEEE Computer Society, (2001)A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference., , , , , , and . DAC, page 520-525. ACM, (2003)A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces., , , , , , , and . ISCAS, page 2837-2840. IEEE, (2008)A Top-Down Microsystems Design Methodology and Associated Challenges ., , , , , and . DATE, page 20292-20296. IEEE Computer Society, (2003)Increasing the number of effective registers in a low-power processor using a windowed register file., , , , , , and . CASES, page 125-136. ACM, (2003)DSP architecture for cochlear implants., , , , , and . ISCAS, IEEE, (2006)A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability., , , , , , , , , and . ISSCC, page 350-351. IEEE, (2008)A 16-bit, low-power microsystem with monolithic MEMS-LC clocking., , , and . ASP-DAC, page 94-95. IEEE, (2006)Supply and Demand Aware Synthetic Data Generation for On-demand Traffic with Real-world Characteristics., , , , and . IWCTS@SIGSPATIAL, page 36-41. ACM, (2017)Hybrid on-chip clocking for sensor nodes., , , , and . SoC, page 129-132. IEEE, (2010)