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An FPGA-Based Embedded System for a Sailing Robot.

, and . DSD, page 830-837. IEEE Computer Society, (2009)

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A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio., , and . FPL, page 1-4. IEEE, (2013)A high-level tool for the design of custom image processing systems., and . DSD, page 346-349. IEEE Computer Society, (2005)FAFNER-Accelerating Nesting Problems with FPGAs., , , , , and . FCCM, page 168-. IEEE Computer Society, (1999)Erlang Inspired Hardware., , and . FPL, page 244-246. IEEE Computer Society, (2010)PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs., , , , and . ISPD, page 49-56. ACM, (2019)A processor for testing mixed-signal cores in System-on-Chip., , , , and . DSD, page 184-191. IEEE Computer Society, (2005)ProHos-1 - A Vector Processor for the Efficient Estimation of Higher-Order Moments., , , and . VECPAR, volume 1215 of Lecture Notes in Computer Science, page 96-107. Springer, (1996)An Alternative SNR Computation Method for ADC Testing., and . DCIS, page 1-6. IEEE, (2019)Flexible hardware acceleration for nesting problems., , , , , and . ICECS, page 345-348. IEEE, (1998)A scalable array for Cellular Genetic Algorithms: TSP as case study., , and . ReConFig, page 1-6. IEEE, (2012)