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A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters.

, , , , и . ISCAS, стр. 1-5. IEEE, (2021)

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Christophe Kunze

Christophe Bobda

Christophe Huber

Christophe Schwarz

Christophe Zerpka

 

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A programmable RFSoC in 16nm FinFET technology for wideband communications., , , , , , , , , и 5 other автор(ы). A-SSCC, стр. 1-4. IEEE, (2017)A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters., , , , и . ISCAS, стр. 1-5. IEEE, (2021)Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters., , , , и . IEEE Open J. Circuits Syst., (2021)A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC., , , , и . ICECS, стр. 1-4. IEEE, (2020)A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET., , , , , , , , , и 10 other автор(ы). VLSI Circuits, стр. 99-100. IEEE, (2018)A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters., , , , , , , , , и 5 other автор(ы). IEEE J. Solid State Circuits, 50 (1): 258-269 (2015)16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 276-277. IEEE, (2017)A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs., , , , , , , , , и . ISSCC, стр. 378-380. IEEE, (2018)16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 280-281. IEEE, (2017)A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC., , , , , , , , , и 3 other автор(ы). VLSI Circuits, стр. 219-220. IEEE, (2018)