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An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.

, , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 252-254. IEEE, (2021)

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Yildiz Sinangil

Mahmut Günay

Mahmut Kara

Mahmut Çalik

Mahmut Sadi

 

Другие публикации лиц с тем же именем

Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics., , , и . A-SSCC, стр. 177-180. IEEE, (2016)An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access., и . ISSCC, стр. 318-319. IEEE, (2013)A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS., , , , , , , , и . IEEE J. Solid State Circuits, 56 (1): 188-198 (2021)Challenges and Directions for Low-Voltage SRAM., , и . IEEE Des. Test Comput., 28 (1): 32-43 (2011)Low-power and application-specific SRAM design for energy-efficient motion estimation.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2012)ndltd.org (oai:dspace.mit.edu:1721.1/75650).A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz., , и . ESSCIRC, стр. 282-285. IEEE, (2008)15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications., , , , , , , и . ISSCC, стр. 242-244. IEEE, (2020)A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V., , и . ISSCC, стр. 260-262. IEEE, (2011)A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation., , , , , , , , , и . VLSIC, стр. 1-2. IEEE, (2014)A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology., , , и . VLSI Circuits, стр. 13-14. IEEE, (2018)