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Chip level security: Why ? How ?. ICECS, page 25-26. IEEE, (2008)Software BIST capabilities of a symmetric cipher., , and . ICECS, page 414-417. IEEE, (2008)Laser-induced fault effects in security-dedicated circuits., , , , , , , , , and 9 other author(s). VLSI-SoC, page 1-6. IEEE, (2014)A New Approach to Control Flow Checking Without Program Modification., , and . FTCS, page 334-343. IEEE Computer Society, (1991)Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems., , , , , , , , and . DDECS, page 1-4. IEEE, (2020)Using Application Profiling based on a Virtual Platform for SoC Fault Tolerance Assessment., , , , and . PRIME, page 225-228. IEEE, (2022)Secure Test with RSNs: Seamless Authenticated Extended Confidentiality., , , and . NEWCAS, page 1-4. IEEE, (2021)Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor., , , , , and . IOLTS, page 125-130. IEEE Computer Society, (2006)Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes., , and . DFT, page 245-253. IEEE Computer Society, (2002)10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard., and . DSD, page 266-269. IEEE Computer Society, (2011)