Author of the publication

A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique.

, , and . APCCAS (2), page 395-398. IEEE, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A new cryogenic CMOS readout structure for infrared focal plane array., , and . IEEE J. Solid State Circuits, 32 (8): 1192-1199 (1997)Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques., , and . IEEE J. Solid State Circuits, 30 (1): 76-80 (January 1995)A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique., , and . APCCAS (2), page 395-398. IEEE, (2002)CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory., and . ISCAS, page 1676-1679. IEEE, (1995)A 3-V 1-GHz Low-Noise Bandpass Amplifier., , and . ISCAS, page 1964-1967. IEEE, (1995)Improvement of pattern learning and recognition capability in ratio-memory cellular neural networks with non-discrete-type Hebbian learning algorithm., and . ISCAS (1), page 629-632. IEEE, (2002)A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors., and . ISCAS (5), page 5079-5082. IEEE, (2005)Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications., and . ISCAS, page 1905-1908. IEEE, (1993)The design of high-performance 128×128 CMOS image sensors using new current-readout techniques., and . ISCAS (5), page 168-171. IEEE, (1999)A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs., and . ISCAS (1), page 47-50. IEEE, (1999)