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Disambiguation of "Tida, Umamaheswara Rao"

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Novel Through-Silicon-Via Inductor-Based On-Chip DC-DC Converter Designs in 3D ICs.

, , and . ACM J. Emerg. Technol. Comput. Syst., 11 (2): 16:1-16:14 (2014)

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Zoubir Tidafi

Umamaheswara Reddy Vemulapati

Yadlapalli Venkateswara Rao

Bharathi Vasudeva Rao

Balakrishna Rao

 

Other publications of authors with the same name

FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration., and . SOCC, page 1-6. IEEE, (2023)Opportunistic through-silicon-via inductor utilization in LC resonant clocks: concept and algorithms., , , and . ICCAD, page 750-757. IEEE, (2014)Dual-Purpose Metal Inter-layer Via Utilization in Monolithic Three-Dimensional (M3D) Integration., and . MWSCAS, page 424-427. IEEE, (2020)Small Footprint 6T-SRAM Design with MIV-Transistor Utilization in M3D-IC Technology., and . ICCD, page 118-125. IEEE, (2023)"Green" On-chip Inductors in Three-Dimensional Integrated Circuits., , , and . ISVLSI, page 571-576. IEEE Computer Society, (2014)Design and Optimization of Magnetic-core Solenoid Inductor for Multi-phase Buck Converter., and . MWSCAS, page 933-936. IEEE, (2020)Novel Through-Silicon-Via Inductor-Based On-Chip DC-DC Converter Designs in 3D ICs., , and . ACM J. Emerg. Technol. Comput. Syst., 11 (2): 16:1-16:14 (2014)Efficient and Scalable MIV-Transistor with Extended Gate in Monolithic 3D Integration., and . MWSCAS, page 187-191. IEEE, (2023)Efficient Metal Inter-Layer Via Utilization Strategies for Three-dimensional Integrated Circuits., and . SoCC, page 195-200. IEEE, (2020)Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration., and . ISQED, page 1-8. IEEE, (2023)