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On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits.

, , and . ITC, page 617-626. IEEE Computer Society, (2004)

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MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing., and . DAC, page 107-110. IEEE Computer Society Press, (1990)Automatic Test Generation Using Quadratic 0-1 Programming., , and . DAC, page 654-659. IEEE Computer Society Press, (1990)Delay Fault Models and Test Generation for Random Logic Sequential Circuits., , and . DAC, page 165-172. IEEE Computer Society Press, (1992)VLSI CAD tool integration using the Ulysses environment., and . DAC, page 55-61. IEEE Computer Society Press, (1986)Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework., , , and . EDAC-ETC-EUROASIC, page 610-617. IEEE Computer Society, (1994)Fault coverage estimation by test vector sampling., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 590-596 (1995)Aliasing Analysis of Spectral Statistical Response Compaction Techniques., and . VLSI Design, page 801-806. IEEE Computer Society, (2006)Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST., and . VLSI Design, page 485-491. IEEE Computer Society, (2007)CMOS Circuit Design for Minimum Dynamic Power and Highest Speed., , and . VLSI Design, page 1035-1040. IEEE Computer Society, (2004)Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program., , and . VLSI Design, page 527-532. IEEE Computer Society, (2003)