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Disambiguation of "Lee, Sae Kyu"

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A multi-chip system optimized for insect-scale flapping-wing robots.

, , , , , , , , and . VLSIC, page 152-. IEEE, (2015)

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Sae Kyung Lee

Sang-Kyu Lee

Han Kyu Lee

Kyu-Yeul Lee

Jae Kyu Lee

 

Other publications of authors with the same name

Evaluation of voltage stacking for near-threshold multicore computing., , and . ISLPED, page 373-378. ACM, (2012)A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET., , , , , and . ESSCIRC, page 158-161. IEEE, (2018)14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications., , , , , and . ISSCC, page 242-243. IEEE, (2017)A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2374-2387 (2017)Sub-uJ deep neural networks for embedded applications., , , and . ACSSC, page 1912-1915. IEEE, (2017)A multi-chip system optimized for insect-scale flapping-wing robots., , , , , , , , and . VLSIC, page 152-. IEEE, (2015)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference., , , , , , , , , and 44 other author(s). ISCA, page 153-166. IEEE, (2021)A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators., , , , , , , , , and . VLSI Circuits, page 34-. IEEE, (2019)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)TuneLogic: Post-silicon tuning of dual-Vdd designs., , and . ISQED, page 394-400. IEEE Computer Society, (2009)