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Disambiguation of "Shimazaki, Yasuhisa"

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An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.

, , , , , , , , , , , , and . ISSCC, page 480-481. IEEE, (2009)

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Yukihiro Yasuhisa

Yasuhisa Ichihashi

Yasuhisa Tsuda

 

Other publications of authors with the same name

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS., , , and . ISSCC, page 384-385. IEEE, (2008)Session 8 overview: Digital PLLs and security circuits., , and . ISSCC, page 140-141. IEEE, (2017)A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D., , , , , , , , , and 3 other author(s). ISSCC, page 54-56. IEEE, (2019)3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV., , , , , , , , , and 2 other author(s). ISSCC, page 58-59. IEEE, (2017)A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power., , , , , , , and . ISSCC, page 240-241. IEEE, (2023)A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor., , , , , , , , , and 14 other author(s). ISSCC, page 2210-2219. IEEE, (2006)Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor., , , , , , , , , and 3 other author(s). ISSCC, page 2200-2209. IEEE, (2006)A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor., , , , , , , and . IEEE J. Solid State Circuits, 40 (1): 186-194 (2005)4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability., , , , , , , and . ISSCC, page 80-81. IEEE, (2016)A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors., , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)