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A 52-dB Self-Interference Rejection Receiver using RF Code-Domain Signal Processing., , , and . CICC, page 1-4. IEEE, (2019)A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation., , , and . IEEE J. Solid State Circuits, 55 (5): 1411-1421 (2020)13.4 A microwave injection-locking outphasing modulator with 30dB dynamic range and 22% system efficiency in 45nm CMOS SOI., and . ISSCC, page 244-245. IEEE, (2016)Virtual-Source Modeling of N-polar GaN MISHEMTS., , , , , , , , , and 1 other author(s). BCICTS, page 1-4. IEEE, (2019)A 108-Gbps, 162-mW Cherry-Hooper Transimpedance Amplifier., , , , and . BCICTS, page 1-4. IEEE, (2020)Improved Signal Integrity at 64 Gbps in a 130-nm SiGe Optical Receiver With Through-Silicon Vias., , , , , and . BCICTS, page 132-135. IEEE, (2022)400 Gbps/λ DP-16QAM O-band Link with SiP TX and RX PICs using only Heterogeneously Integrated Lasers and SOAs for Optical Gain., , , , , , , , , and 7 other author(s). OFC, page 1-3. IEEE, (2024)Design methodology of high performance on-chip global interconnect using terminated transmission-line., , , , , , , and . ISQED, page 451-458. IEEE Computer Society, (2009)A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOS., , and . ESSCIRC, page 189-192. IEEE, (2016)A 111-149-GHz, Compact Power-combined Amplifier With 17.5-dBm Psat, 16.5% PAE in 22-nm CMOS FD-SOI., and . ESSCIRC, page 453-456. IEEE, (2022)