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Fast system-level exploration of memory architectures driven by energy-delay metrics.

, , , and . ISCAS (4), page 502-505. IEEE, (2001)

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A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 177-196. Springer, (2006)A light-weight Network-on-Chip architecture for dynamically reconfigurable systems., , , and . ICSAMOS, page 49-56. IEEE, (2008)An adaptive genetic algorithm for dynamically reconfigurable modules allocation., , , and . VLSI-SoC, page 128-133. IEEE, (2007)Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology., , , and . FPT, page 293-296. IEEE, (2006)Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs., , , , , and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 179-192. Springer, (2007)An approach to a design for testability personal consultant., , , and . Microprocessing and Microprogramming, 30 (1-5): 405-412 (1990)Optimization techniques for multiple output function synthesis., , and . EURO-DAC, page 545-551. EEE Computer Society, (1991)Two-Dimensional Sequential Array Architectures: Design for Testability Approaches., , and . ISCAS, page 81-84. IEEE, (1994)An Output/State Encoding for Self-Checking Finite State Machine., and . ISCAS, page 2136-2139. IEEE, (1995)Data Path Testability Analysis Based on BDDs., , and . ISCAS, page 2012-2014. IEEE, (1995)