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Networks on Chips: from research to products., , , , , and . DAC, page 300-305. ACM, (2010)Synthesis of networks on chips for 3D systems on chips., , , and . ASP-DAC, page 242-247. IEEE, (2009)3.5-D integration: A case study., , , , and . ISCAS, page 2087-2090. IEEE, (2013)A DRAM Centric NoC Architecture and Topology Design Approach., , , and . ISVLSI, page 54-59. IEEE Computer Society, (2011)Benchmarking TensorFlow Lite Quantization Algorithms for Deep Neural Networks., , and . SACI, page 221-226. IEEE, (2022)A method to remove deadlocks in Networks-on-Chips with Wormhole flow control., , , and . DATE, page 1625-1628. IEEE Computer Society, (2010)SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips., , , and . DATE, page 9-14. IEEE, (2009)CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers., , , , , and . NOCS, page 67-74. IEEE Computer Society, (2012)A floorplan-aware interactive tool flow for NoC design and synthesis., , , , , and . SoCC, page 379-382. IEEE, (2009)A distributed interleaving scheme for efficient access to WideIO DRAM memory., , and . CODES+ISSS, page 103-112. ACM, (2012)