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Disambiguation of "Mishchenko, Alan"

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Board-level multiterminal net assignment.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 130-135. ACM, (2002)

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Oleksiy Mishchenko

Safwat Alani

Maia Alandjiyska

Yilmaz Alan

Viola Alanku

 

Other publications of authors with the same name

Rewriting Environment for Arithmetic Circuit Verification., , , , and . LPAR, volume 57 of EPiC Series in Computing, page 656-666. EasyChair, (2018)Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis., , , and . ASP-DAC, page 395-402. IEEE, (2022)Incremental ATPG methods for multiple faults under multiple fault models., , , and . ISQED, page 177-180. IEEE, (2015)Invariant-Strengthened Elimination of Dependent State Elements., , , , and . FMCAD, page 1-9. IEEE, (2008)A theory of nondeterministic networks., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 977-999 (2006)m-Inductive Property of Sequential Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (6): 919-930 (2016)Three-Input Gates for Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract)., , , , , , and . BCB, page 623-624. ACM, (2014)Scalable min-register retiming under timing and initializability constraints., , and . DAC, page 534-539. ACM, (2008)A Boolean Paradigm in Multi-Valued Logic Synthesis., and . IWLS, page 173-177. (2002)