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A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder., , и . MWSCAS, стр. 241-244. IEEE, (2023)A ROM-less direct digital frequency synthesizer by using trigonometric quadruple angle formula., , и . ICECS, стр. 65-68. IEEE, (2002)67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process., и . ISCAS, стр. 1-4. IEEE, (2021)Improved design of C2PL 3-2 compressors with less transistor count., , и . ISCAS, стр. 61-64. IEEE, (2000)Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process., , и . ICICDT, стр. 24-27. IEEE, (2022)100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*., и . APCCAS, стр. 98-101. IEEE, (2020)A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture., , , , , , , , и . APCCAS, стр. 46-49. IEEE, (2022)A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process., , , , , , , и . Integr., (мая 2023)Power-saving nano-scale DRAMs with an adaptive refreshing clock generator., , , и . ISCAS, стр. 612-615. IEEE, (2008)A Drive Circuit for Piezoelectric Devices with Low Harmonics Content., , и . ISCAS, стр. 1093-1096. IEEE, (2009)