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2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing., и . ISCAS, IEEE, (2006)A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators., , , , , и . VLSIC, стр. 1-2. IEEE, (2014)A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control., , , , и . VLSIC, стр. 182-183. IEEE, (2012)A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW., , , , , , , , и . VLSIC, стр. 1-2. IEEE, (2014)A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links., , , , и . IEEE J. Solid State Circuits, 49 (10): 2243-2258 (2014)A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS., , , , , , , , и . ISSCC, стр. 102-104. IEEE, (2018)A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity., , , и . VLSIC, стр. 188-189. IEEE, (2012)A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC., , , , и . IEEE J. Solid State Circuits, 50 (4): 867-881 (2015)A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC., , , и . ISSCC, стр. 242-244. IEEE, (2012)A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery., , , и . ISSCC, стр. 440-442. IEEE, (2011)