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Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (7): 3538-3542 (July 2024)

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Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (7): 3538-3542 (July 2024)