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Disambiguation of "Iyer, Subramanian S."

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Architecting Waferscale Processors - A GPU Case Study.

, , , , , and . HPCA, page 250-263. IEEE, (2019)

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Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Pallavi Subramanian

 

Other publications of authors with the same name

Hybrid Obfuscation of Chiplet-Based Systems., , , , and . DAC, page 1-6. IEEE, (2023)Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration., , , and . JETC, 13 (3): 45:1-45:21 (2017)An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices., and . ISSCC, page 434-435. IEEE, (2023)Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric., and . ISQED, page 315. IEEE, (2021)Designing a 2048-Chiplet, 14336-Core Waferscale Processor., , , , , , , , , and . DAC, page 1183-1188. IEEE, (2021)Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications., , , , , , , , , and 3 other author(s). IRPS, page 2. IEEE, (2015)A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 406-407. IEEE, (2008)Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM., , , , , and . VLSIC, page 146-147. IEEE, (2012)Integrated neural interfaces., , , , , , , , and . MWSCAS, page 1045-1048. IEEE, (2017)