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A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer., , , и . A-SSCC, стр. 187-190. IEEE, (2018)A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit., , и . VLSIC, стр. 140-. IEEE, (2015)19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection., , и . ISSCC, стр. 326-327. IEEE, (2016)A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning., , , , и . ISSCC, стр. 308-310. IEEE, (2018)A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology., и . ISCAS, стр. 1-4. IEEE, (2017)Impact of NBTI on SRAM Read Stability and Design for Reliability., , и . ISQED, стр. 210-218. IEEE Computer Society, (2006)TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique., , и . ISQED, стр. 59-64. IEEE Computer Society, (2005)Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance., , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (9): 1203-1211 (2009)A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing., , , , , и . CICC, стр. 1-4. IEEE, (2019)SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data., , и . CICC, стр. 1-4. IEEE, (2014)