( en | de | ru )

 

Disambiguation of "Roy, Sourav"

Author of the publication

copydeleteadd this publication to your clipboard
A dual band microstrip antenna integrated with rectangular DRA for uplink and downlink C band communication.

, , and . RAIT, page 1-4. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sourav Dutta

Sourav Chakraborty

Roy Hornig

Beschreibung mikro-rheologischer Vorgänge und resultierender Verbundstrukturen beim Elastomermischprozeß im Innenmischer durch rheologische Untersuchungen. NA Halle-Wittenberg, (2009)

Trina Roy

Smritindu Roy

 

Other publications of authors with the same name

Latency Critical Operation in Network Processors., , , , , and . Hot Interconnects, page 63-67. IEEE, (2019)Self-timed Sensors for Detecting Static Optical Side Channel Attacks., , , and . ISQED, page 1-6. IEEE, (2022)A dual band microstrip antenna integrated with rectangular DRA for uplink and downlink C band communication., , and . RAIT, page 1-4. IEEE, (2018)PLAKE: PUF-Based Secure Lightweight Authentication and Key Exchange Protocol for IoT., , , , , and . IEEE Internet Things J., 10 (10): 8547-8559 (May 2023)VLSI Architectures of Forward Kinematic Processor for Robotics Applications., , and . CoRR, (2024)High level energy modeling of controller logic in data caches., , , , , , and . ACM Great Lakes Symposium on VLSI, page 45-50. ACM, (2014)Dynamic Sharing of On-Chip Scratchpad Memory on Embedded Platforms., , and . ISED, page 120-124. IEEE, (2012)PUF based Lightweight Authentication and Key Exchange Protocol for IoT., , , , , and . SECRYPT, page 698-703. SCITEPRESS, (2021)H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors.. VLSI Design, page 553-558. IEEE Computer Society, (2009)Leveraging Virtual Prototype Models for Hardware Verification of an Accelerated Network Packet Processing Engine., , , and . MTV, page 15-19. IEEE Computer Society, (2015)