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Disambiguation of "Yoshida, Toyohiko"

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A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface.

, , , , , , , and . ICCD, page 203-210. IEEE Computer Society, (1994)

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Takuro Yoshida

Daisuke Yoshida

Shingo Yoshida

Kazuhiko Yoshida

Ruriko Yoshida

 

Other publications of authors with the same name

A 32-bit microprocessor with high performance bit-map manipulation instructions., , , , , , and . ICCD, page 406-409. IEEE, (1989)A dual-issue RISC processor for multimedia signal processing., , , , and . ICASSP, page 591-594. IEEE Computer Society, (1997)A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores., , , , , , , , , and 5 other author(s). CICC, page 95-98. IEEE, (1999)A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications., , , , , , , , , and 1 other author(s). CICC, page 169-172. IEEE, (1998)Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor., , , and . ICCD, page 208-216. IEEE Computer Society, (1996)Evaluation of processor code efficiency for embedded systems., , , , , and . ICS, page 229-235. ACM, (2001)A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface., , , , , , , and . ICCD, page 203-210. IEEE Computer Society, (1994)Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding., , , and . J. VLSI Signal Process., 18 (2): 155-165 (1998)A strategy for avoiding pipeline interlock delays in a microprocessor., , , and . ICCD, page 14-19. IEEE Computer Society, (1990)A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100., , , , and . COMPCON, page 30-35. IEEE Computer Society, (1988)