Author of the publication

Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (8): 2160-2170 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3435-3444 (2018)Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (8): 2160-2170 (2017)