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Compiler-managed register file protection for energy-efficient soft error reduction.

, and . ASP-DAC, page 618-623. IEEE, (2009)

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Improving performance of loops on DIAM-based VLIW architectures., , , and . LCTES, page 135-144. ACM, (2014)Evaluator-executor transformation for efficient pipelining of loops with conditionals., , and . ACM Trans. Archit. Code Optim., 10 (4): 62:1-62:23 (2013)Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (8): 2799-2802 (2016)Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (12): 1978-1988 (2017)Accurate Prediction of ReRAM Crossbar Performance Under I-V Nonlinearity and IR Drop., , , , and . ICCD, page 9-16. IEEE, (2022)SparTANN: sparse training accelerator for neural networks with threshold-based sparsification., , and . ISLPED, page 211-216. ACM, (2020)Compiler-managed register file protection for energy-efficient soft error reduction., and . ASP-DAC, page 618-623. IEEE, (2009)Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks., , , and . ICCD, page 105-112. IEEE Computer Society, (2017)Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware., , , , , and . DAC, page 1-6. IEEE, (2020)Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture., , , , , and . ARC, volume 7199 of Lecture Notes in Computer Science, page 40-52. Springer, (2012)