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Complexity in an Industrial flyback converter., , , and . Journal of Circuits, Systems, and Computers, 5 (4): 627-634 (1995)A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2024)Cellular neural networks to explore complexity., , , and . Soft Comput., 1 (3): 120-136 (1997)An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits.. ICECS, page 1553-1556. IEEE, (2001)Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW., , , , and . ESSCIRC, page 248-251. IEEE, (2007)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 1158-1170 (April 2024)A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration., , , and . CICC, page 317-320. IEEE, (2007)A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer., , and . CICC, page 429-432. IEEE, (2003)40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW., , , , and . IEEE J. Solid State Circuits, 43 (7): 1648-1656 (2008)A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF., , , and . ISSCC, page 148-150. IEEE, (2012)