Author of the publication

Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1351-1360 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Mini-batch Serialization: CNN Training with Inter-layer Data Reuse., , , , , and . CoRR, (2018)NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime., , and . ISLPED, page 253-258. ACM, (2010)Reducing Load Latency with Cache Level Prediction., and . CoRR, (2021)Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism., , , , , and . IEEE Micro, 32 (3): 79-87 (2012)Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1351-1360 (2016)A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC., , , and . DAC, page 850-855. ACM, (2012)Architectural Support for the Stream Execution Model on General-Purpose Processors., , , , and . PACT, page 3-12. IEEE Computer Society, (2007)Reducing Load Latency with Cache Level Prediction., and . HPCA, page 648-661. IEEE, (2022)CLEAN-ECC: high reliability ECC for adaptive granularity memory system., , , , and . MICRO, page 611-622. ACM, (2015)Predicting Future-System Reliability with a Component-Level DRAM Fault Model., and . MICRO, page 944-956. ACM, (2023)